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HIP0061
December 1997
60V, 3.5A, 3-Transistor Common Source ESD Protected Power MOSFET Array
Description
The HIP0061 is a power MOSFET array that consists of three matched N-Channel enhancement mode MOS transistors connected in a common source configuration. The advanced Harris PASIC2 process technology used in this product utilizes efficient geometries that provides outstanding device performance and ruggedness. The HIP0061 is designed to integrate three power devices in one chip thus providing board layout area and heat sink savings for applications such as Motor Controls, Lamps, Solenoids and Resistive Loads.
Features
* Three 3.5A Power MOS N-Channel Transistors * Output Voltage to 60V * rDS(ON) . . . . . 0.225 Max Per Transistor at VGS = 10V * Pulsed Current . . . . . . . . . . . . . . . . 10A Each Transistor * Avalanche Energy . . . . . . . . . . 100mJ Each Transistor * Grounded Tab Eliminates Heat Sink Isolation
Applications
* Automotive * Appliance * Industrial Control * Robotics * Relay, Solenoid, Lamp Drivers
Symbol
DRAIN1 2 DRAIN2 5 DRAIN3 7
GATE1
GATE2 3
GATE3 6
Ordering Information
PART NUMBER HIP0061AS1 TEMP. RANGE (oC) -40 to 125 PACKAGE 7 Ld Staggered Vertical SIP 7 Ld Gullwing SIP PKG. NO.
1
4
Z7.05C
SOURCE, TAB
HIP0061AS2
-40 to 125
Z7.05B
Pinouts
HIP0061AS1 (SIP - VERTICAL) TOP VIEW HIP0061AS2 (SIP - GULLWING) TOP VIEW
7 6 5 4 3 2 1
DRAIN3 GATE3 DRAIN2 SOURCE GATE2 DRAIN1 GATE 1 TAB
7 6 5 4 3 2 1
DRAIN3 GATE3 DRAIN2 SOURCE GATE2 DRAIN1 GATE 1
TAB TAB (SOURCE) INTERNALLY CONNECTED TO PIN 4 TAB (SOURCE) INTERNALLY CONNECTED TO PIN 4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
3982.3
1
HIP0061
Absolute Maximum Ratings
TA = 25oC
Thermal Information
Thermal Resistance (Typical, Note 4) JA (oC/W) JC (oC/W) SIP-Vertical Package . . . . . . . . . . . . . 55 3 SIP-Gullwing Package . . . . . . . . . . . . 55 3 Maximum Junction Temperature, TJ . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range, TSTG . . . . -55oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
Drain to Source Voltage, VDS (Over Operating Junction and Case Temperature Range) . . . . 60V Drain to Gate Voltage, VDGR . . . . . . . . . . . . . . . . . . . . . . . . . . . 60V Gate to Source Voltage, VGS . . . . . . . . . . . . . . . . . . . . . . .-15, +20V Pulsed Drain Current, IDM, Each Output, All Outputs on at VGS = 10V (Notes 1, 2) . . . . . . . . . . . . . . . . 10A Continuous Source to Drain Diode Current, ISD at VGS = 10V (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5A Continuous Drain Current, IDS, Each Output, All Outputs on at VGS = 10V (Note 2) . . . . . . . . . . . . . . . . . . 3.5A Single Pulse Avalanche Energy, EAS (Note 3) . . . . . . . . . . . . 100mJ
Die Characteristics
Back Side Potential . . . . . . . . . . . . . . . . . . . . . . . . . V- (Source, Tab)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 125oC Drain to Source On-State Voltage Range . . . . . . . . . . . . 5V to 10V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Pulse width limited by maximum junction temperature. 2. Drain current limited by package construction. 3. VDD = 25V, Start TJ = 25oC, L = 15mH, RGS = 50, IPEAK = 3.5A. See Figures 1, 2, 12, and 13. 4. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETERS
TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS TEST CONDITIONS ID = 100A, VGS = 0V TC = -40o C to 125oC TC = 25o C MIN 60 1.8 TC = 25o C TC = 125o C TC = 25oC TC = 125oC TC = 25oC TC = 125oC TC = 25oC VDS = 50V, VGS = 10V, ID = 2A See Figures 16, 17 TYP 70 2.3 0.215 0.365 0.275 0.465 95 2.5 10 25 18 12 8.0 0.7 3.5 MAX 2.7 1 10 100 -100 0.265 0.425 0.320 0.5 9.5 1.0 4.0 UNITS V V V A A nA nA % S ns ns ns ns nC nC nC
Drain to Source Breakdown Voltage
Gate Threshold Voltage Zero Gate Voltage Drain Current
VGS(TH) IDSS
VGS = VDS, ID = 250A VDS = 60V VGS = 0V VDS = 0V, VGS = 20V VDS = 0V, VGS = -15V VGS = 10V, ID = 3.5A VGS = 10V, ID = 3.5A VGS = 5V, ID = 2A VGS = 5V, ID = 2A
Forward Gate Current, Drain Short Circuited to Source Reverse Gate Current, Drain Short Circuited to Source Drain to Source On Resistance (Note 5)
IGSSF IGSSR rDS(ON)
Drain to Source On Resistance Matching Forward Transconductance (Note 5) Turn-On Delay Time (Note 6) Rise Time (Note 6) Turn-Off Delay Time (Note 6) Fall Time (Note 6) Total Gate Charge (Note 6) Gate-Source Charge (Note 6) Gate-Drain Charge (Note 6)
rDS(ON) gfs td(ON) tr td(OFF) tf Qg(TOT) Qgs Qgd
VGS = 10V, ID = 3.5A VDS = 10V, ID = 1A
VDD = 30V, RL = 15, VGS = +10V, ID = 2A, RG = 50 See Figure 14
2
HIP0061
Electrical Specifications
PARAMETERS Short-Circuit Input Capacitance, Common Source Short-Circuit Output Capacitance, Common Source Short-Circuit Reverse Transfer Capacitance, Common Source TC = 25oC, Unless Otherwise Specified (Continued) SYMBOL CISS COSS CRSS TEST CONDITIONS VDS = 25V, VGS = 0V f = 1MHz MIN TYP 142 107 24 MAX UNITS pF pF pF
Source-Drain Diode Ratings and Specifications
PARAMETERS Diode Forward Voltage (Note 5) Reverse Recovery Time NOTES: 5. Pulse test: Pulse width 300s, duty cycle 2%. 6. Independent of operating temperature. SYMBOL VSD trr TEST CONDITIONS ISD = 2A, VGS = 0V ISD = 2A, dISD/dt = 100A/s MIN TYP 0.9 50 MAX 1.1 UNITS V ns
Typical Performance Curves
10
10s ID , DRAIN CURRENT (A)
10 10s 100s 100s 1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) TC = 105oC TJ = MAX RATED 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 100 10ms 100ms DC 1ms
ID , DRAIN CURRENT (A)
100s 1ms 1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) TC = 25oC TJ = MAX RATED 1 10 VDS , DRAIN VOLTAGE (V) 100 10ms 100ms DC
0.1
0.1
FIGURE 1A. 25oC SAFE-OPERATING AREA CURVE
FIGURE 1B. 105oC SAFE-OPERATING AREA CURVE
50 IAS, AVALANCHE CURRENT (A) 10
ID , DRAIN CURRENT (A)
STARTING TJ = 25oC 10 STARTING TJ = 125oC
10s 1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) TC = 125oC TJ = MAX RATED 1 100s 1ms 10ms 100ms DC 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 100
5
0.1
1 0.001
0.01 0.1 tAV , TIME IN AVALANCHE (ms)
1.0
FIGURE 1C. 125oC SAFE-OPERATING AREA CURVE
FIGURE 2. UNCLAMPED INDUCTIVE-SWITCHING
3
HIP0061 Typical Performance Curves
10.0 VGS = 10V VGS = 8V VGS = 6V
(Continued)
20 VDS = 15V VGS = 5V ID, DRAIN CURRENT (A) 15 -40oC 25oC 125oC
ID, DRAIN CURRENT (A)
7.5
5.0 VGS = 4V
10
2.5 PULSE DURATION = 300s, TC = 25oC 0 0 2 4 6 8 10 VDS, DRAIN TO SOURCE VOLTAGE (V)
5
0 0
2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V)
10
FIGURE 3. TYPICAL SATURATION CHARACTERISTICS
FIGURE 4. TYPICAL TRANSFER CHARACTERISTICS
rDS(ON), NORMALIZED ON RESISTANCE
2.5 PULSE DURATION = 300s, VGS = 10V, ID = 3.5A 2.0 NORMALIZED BVDSS
1.2 ID = 100A 1.1
1.5
1.0
1.0
0.5
0.9
0 -75
-25
25
75
125
175
0.8 -75
-25
TJ, JUNCTION TEMPERATURE (oC)
25 75 125 TJ, JUNCTION TEMPERATURE (oC)
175
FIGURE 5. NORMALIZED rDS(ON) vs JUNCTION TEMPERATURE
FIGURE 6. NORMALIZED BVDSS vs JUNCTION TEMPERATURE
2.0 VGS = VDS, ID = 250A VGS, GATE-SOURCE VOLTAGE (V) VGS(TH), NORMALIZED 1.5
12 VDS = 50V VDS = 30V 8 VDS = 20V
1.0
4
0.5
ID = 2.0A, TC = 25oC 0 0 2 4 6 Q, GATE CHARGE (nC) 8 10
0 -75
-25
25
75
125
175
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 7. NORMALIZED VGS(TH) vs JUNCTION TEMPERATURE
FIGURE 8. GATE-SOURCE VOLTAGE vs GATE CHARGE
4
HIP0061 Typical Performance Curves
750
(Continued)
VGS = 0V, f = 1MHz, TC = 25oC ID , DRAIN CURRENT (A)
5
C, CAPACITANCE (pF)
600
4
450 CISS COSS CRSS
3
VGS = 10V VGS = 5V
300
2
150
1
0 0 5 10 15 20 VDS, DRAIN TO SOURCE VOLTAGE (V) 25
0 25 50 75 100 125 150 TC, CASE TEMPERATURE (oC)
FIGURE 9. TYPICAL CAPACITANCE vs VOLTAGE
FIGURE 10. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
ZJC, NORMALIZED THERMAL IMPEDANCE
10
TC = 25oC
1
D = 1.0 0.5 0.2 0.1 0.05 0.02 0.01 SINGLE PULSE
0.1
NOTES: 1. DUTY FACTOR, D = t1/t2 2. PEAK TJ = PDM x (ZJC) +TC 10-4 10-3 t, RECTANGULAR PULSE DURATION (s) 10-2 10-1
10-6
10-5
FIGURE 11. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
Test Circuits and Waveforms
tP VDS VGS L RG VGS + VDD ID 0 BVDSS tAV
10 V 0 IAS
DUT
0V
tP
ID 0.01
VDS 0
FIGURE 12. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 13. UNCLAMPED ENERGY WAVEFORMS
5
HIP0061 Test Circuits and Waveforms
VDD
tON td(ON)
tOFF td(OFF) tr tf 90%
RL VDS VGS DUT 0V RGS
VDS
90%
10%
10%
90% VGS 10% 50% PULSE WIDTH 50%
FIGURE 14. RESISTIVE SWITCHING TEST CIRCUIT
FIGURE 15. RESISTIVE SWITCHING WAVEFORMS
CURRENT REGULATOR + 10V BATTERY 0.2F 25k 0.1F
+VDS Qg SAME TYPE AS DUT 10V
Qgs
Qgd
DUT 0 IGS
VG
CHARGE
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. BASIC GATE CHARGE WAVEFORM
6
HIP0061 PSPICE Model Listing Device Model Netlist for the HIP0061 Power MOSFET Array
*Rev: 6/12/95 .SUBCKT HIP0061 1 2 3 4 5 6 7 X1 8 1 11 4 HIP0061_1 LS1 2 8 7.5n X2 9 3 11 4 HIP0061_1 LS2 5 9 7.5n X3 10 6 11 4 HIP0061_1 LS3 7 10 7.5n LS4 4 11 7.5n .ENDS .SUBCKT HIP0061_1 3 2 11 9 MOS1 4 2 1 1 NMOS1 JFET 13 1 4 J1 D1 5 6 D1 DBODY 1 13 D2 DBREAK 3 7 D3 DSUB 9 13 D4 DESD1 2 12 D5 DESD2 15 12 D5 VBREAK 7 1 DC 90 C21 2 1 750P C23 2 13 45P C24 2 4 1100P RDRAIN 13 14 9.0e-02 LDRAIN 14 3 7.5n RSOURCE 1 15 17.5e-03 LSOURCE 15 11 7.5n FDSCHRG 4 2 VMEAS 1.0 E41 5 15 4 1 1.0 VPINCH 6 8 DC 10.0 VMEAS 8 15 DC 0.0 .MODEL NMOS1 NMOS LEVEL=3 (VTO=2.75 TOX=5e-08 KP=3.150e-03 PHI=0.65 GAMMA=2.55 + VMAX=6.42e+07 NSUB=4.33e+16 THETA=0.60973 ETA=0.0015 KAPPA=1.275 + L=1u W=3050u) .MODEL J1 NJF (VTO=-15.0 BETA=10.736 LAMBDA=1.15e-02 PB=0.5848 IS=+1.0e-13 + RD=3.53e-02 ALPHA=0.2) .MODEL D1 D (IS=1.0e-15 N=0.03 RS=1.0) .MODEL D2 D (IS=3.0e-13 RS=2.5e-03 TT=20N CJO=350e-12) .MODEL D3 D (IS=1.0e-13 N=1.0 RS=2.0) .MODEL D4 D (IS=1.0e-13 RS=2.0e-03 CJO=80e-12) .MODEL D5 D (IS=1.0e-15 RS=1.0e-03 CJO=2.5e-12) .ENDS
NOTE: For further discussion of the PSPICE PowerFET macromodel consult Spicing-Up SPICE II Software for Power MOSFET Modeling, Harris Application Note AN8610.
7
HIP0061 Single-In-Line Plastic Packages (SIP)
-AE L2 A 0.006 -B- (0.15) C2
Z7.05B
7 LEAD PLASTIC SINGLE-IN-LINE PACKAGE SURFACE MOUNT "GULLWING" LEAD FORM INCHES SYMBOL MIN 0.170 0.048 0.350 0.395 0.310 0.310 0.549 0.068 0.045 MAX 0.180 0.055 0.370 0.405 0.569 0.088 0.055 MILLIMETERS MIN 4.32 1.22 8.89 10.04 7.88 7.88 13.95 1.72 1.15 MAX 4.57 1.39 9.39 10.28 14.45 2.24 1.40 NOTES 5 4 5, 6, 7 5 Rev. 2 12/95 NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-169AC, Issue A. 2. Controlling dimension: Inch. 3. Dimensioning and tolerance per ANSI Y14.5M-1982. 4. Gauge plane L3 is parallel to heatslug plane. 5. Dimensions include lead finish. 6. Leads are not allowed above the datum -B- . 7. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum "b" by more than 0.003'' (0.08mm).
D -CL
HEATSLUG PLANE 0.00 - 0.0098 (0.00 - 0.25) L1
A C2 D E D1
PIN #1
c e b
0.010 (0.25) M B A M CM L3 0.004 (0.10) 0o- 8o
E1 L L1 L2 L3
0.030 BSC 0.028 0.018 0.034 0.024
0.76 BSC 0.71 0.46 0.86 0.60
E1
0.450 (11.43) MIN
b c e
0.350 (8.89) MIN
0.050 BSC
1.27 BSC
D1
0.609 (15.46) MIN BACK VIEW 0.129 (3.27) TYP 0.030 (0.76) TYP
e
LAND PATTERN
8
HIP0061 Single-In-Line Plastic Packages (SIP)
0.006 (0.15) A D -BOP D1 E2 F
Z7.05C
7 LEAD PLASTIC SINGLE-IN-LINE PACKAGE STAGGERED VERTICAL LEAD FORM INCHES SYMBOL A B C D MIN 0.170 0.028 0.018 0.395 0.198 0.595 0.350 MAX 0.180 0.034 0.024 0.405 0.202 0.605 0.370 MILLIMETERS MIN 4.32 0.71 0.46 10.04 5.03 15.11 8.89 MAX 4.57 0.86 0.60 10.28 5.13 15.37 9.39 NOTES 3, 4 3 -
E E1 L1
HEADER BOTTOM
D1 E E1 E2 e
0.110 BSC 0.050 BSC 0.200 BSC 0.169 BSC 0.300 BSC 0.048 0.150 0.600 0.147 0.055 0.176 0.620 0.152
2.79 BSC 1.27 BSC 5.08 BSC 4.29 BSC 7.62 BSC 1.22 3.81 15.24 3.73 1.39 4.47 15.74 3.86 3 3 Rev. 0 6/95
L
e
B
-A-
e1 e2
e3
7 PLACES 0.010 (0.25) M A BM
e1
C ALL LEADS
e2
e3 F L
A
0.024 (0.61) M
L1 OP NOTES:
1. Controlling dimension: INCH. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimensions include lead finish. 4. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall not cause lead width to exceed maximum "B" by more than 0.003 inches (0.08mm).
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
9

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